1. Field of the Invention
The present invention pertains generally to integrated circuits, and more particularly, the present invention relates to integrated circuits having high quality inductors.
2. Related Art
Inductors are fabricated on to integrated circuits (IC) to minimize external components, to increase design flexibility and to reduce the overall cost of the IC. Generally, on-chip inductors are formed as a spiral structure which lies in a metal layer of the IC. Most IC applications require an inductor with a high Q (quality factor). The Q of an inductor is proportional to the magnetic energy stored in the inductor divided by the energy dissipated in the inductor in one oscillation cycle. The amount of magnetic energy stored in an inductor is directly proportional to the value of inductance of the inductor. The amount of energy dissipated in the inductor depends on resistive elements associated with the inductor.
In differential signal operation (i.e. two signals with the same magnitude, but with 180-degree phase difference), ICs generally use single mode asymmetric inductors in pairs, which are placed symmetrically on a common dielectric surface. To avoid unwanted electrical and magnetic coupling, the asymmetric inductors are placed far apart occupying more area. Differentially excited symmetric inductors, on the other hand, are area-efficient and have higher Q than single-ended structures. FIG. 1 is a top view of a typical symmetric inductor 100 including five turns. The symmetric inductor is designed for differential excitation and when excited differentially, currents in the adjacent turns follow in the same direction aiding the magnetic fields, which provides a higher inductance per area. Typically, the symmetric inductor structures are developed on one layer with an underpass layer.
What is needed is a multi-layer symmetric inductor having a higher Q when compared to single plane differential inductors, a lower self-resonant frequency and a minimal area occupancy.